Design Verification Tool Automates Test Generation

June 8th, 2007

MathWorks Simulink Design Verifier generates tests and proves design properties for Simulink and Stateflow models. Model-Based Design is becoming widely used for embedded system development, moving from R&D and proof-of-concept projects into production programs

Engineers can generate test inputs that satisfy standard coverage objectives as well as user-defined test objectives and requirements. These test inputs can also be combined with tests defined using measured data so that simulations are testing against model coverage, requirements, and real-world scenarios.

For property proving, engineers can directly capture design requirements and performance objectives as properties in their Simulink or Stateflow models. Simulink Design Verifier mathematically proves whether those properties are satisfied and, if not, provides counterexamples that would violate the properties. As a result, engineers can find design flaws, unsatisfied requirements, and unreachable states or logic that would be difficult to uncover using simulation alone.

Simulink Design Verifier is available immediately for the Microsoft Windows and Linux platforms. U.S. list prices start at $8,000.

Entry Filed under: Simulation